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Renesas introduces 3nm chiplet technology for R-Car X5H automotive SoC
Wednesday, February 4, 2026 at 08:10 PM
Renesas has announced new technology for its R-Car X5H automotive SoC, which utilizes a chiplet architecture on a 3nm process node and achieves ASIL-D functional safety compliance.
Context
Renesas has introduced groundbreaking 3nm chiplet technology for its R-Car X5H automotive SoC, the industry’s first multi-domain processor built at this scale. Utilizing Universal Chiplet Interconnect Express (UCIe), the platform consolidates ADAS, infotainment, and gateway functions onto a single chip while reducing power consumption by 35% compared to 5nm predecessors. This move is vital for centralized software-defined vehicle (SDV) architectures, offering hardware-based isolation to meet strict ASIL-D safety standards.
The SoC delivers massive compute density with 32 Arm Cortex-A720AE cores and 400 TOPS of integrated AI performance, scaleable by 4x via external chiplets. Recent disclosures at ISSCC 2026 highlighted proprietary power gating and memory technologies that ensure automotive-grade reliability for these high-density 3nm nodes. Tier 1 partners like Bosch and ZF are already validating the platform. Silicon samples are currently shipping to select customers, with volume production targeted for the second half of 2027.
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