News
DNP Develops 10nm Nanoimprint Template for 1.4nm Equivalent Semiconductors
Monday, December 8, 2025 at 08:39 PM
Dai Nippon Printing (DNP) announced the development of a nanoimprint lithography (NIL) template featuring a 10nm circuit line width. This template utilizes double patterning and is designed to support the miniaturization of advanced NAND and logic semiconductors, corresponding to the 1.4nm technology generation.
Context
Japanese tech giants Dai Nippon Printing (DNP) and Canon are advancing a new 1.4nm semiconductor manufacturing process using nanoimprint lithography (NIL), aiming to revolutionize chip production. DNP is set to mass-produce core components for this technology by 2027, with Canon developing the NIL equipment. This innovative approach promises to significantly reduce manufacturing costs and power consumption, potentially making advanced chip production more accessible beyond current extreme ultraviolet (EUV) lithography methods. The technology is claimed to enable manufacturing at 1/10 the power of current leading processes, which could meaningfully lower AI chip production costs.
DNP has a ¥30 billion capital investment plan for FY2026-FY2028, with a pilot line scheduled for completion by the end of 2025. Industry adoption decisions are anticipated between late 2025 and the first half of 2026, with full-scale mass production expected to ramp up from 2028. This collaboration positions both companies to become critical players in the next generation of high-performance, energy-efficient semiconductor manufacturing, particularly for AI chips.
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