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Synopsys achieves 10.6 Gbps LPDDR6 performance on 2nm process node
Wednesday, March 4, 2026 at 12:50 AM
Synopsys has successfully demonstrated silicon results for LPDDR6 IP achieving 10.6 Gbps read/write speeds on a 2nm process node to address SDRAM bottlenecks in advanced SoC designs.
Context
Synopsys has achieved a critical milestone for the AI and mobile industries by validating its LPDDR6 IP at 10.6 Gbps on TSMC’s 2nm (N2P) process node. This achievement directly addresses the memory bandwidth bottlenecks currently limiting advanced AI system-on-chips (SoCs). By demonstrating stable silicon results at the initial maximum speed defined by the new JEDEC LPDDR6 standard, Synopsys provides a foundational building block for the next generation of power-efficient, high-performance computing.
The transition to LPDDR6 offers a 1.5x speed improvement over the previous LPDDR5X generation. For investors, this development is significant as major chipmakers race to integrate faster memory into mobile, automotive, and edge AI devices. With the LPDDR6 standard finalized in 2025, these latest results confirm the ecosystem is on track for commercial deployment starting in 2026, solidifying the role of Synopsys as a primary IP provider for the industry-wide shift to 2nm manufacturing.
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