Rumor
Intel Nova Lake compute tile die size reported under 100 square millimeters
Tuesday, February 10, 2026 at 03:41 AM
Reports indicate that the core compute tile of Intel Nova Lake processors will feature a die size of less than 100 square millimeters, while the variant incorporating bLLC is expected to measure approximately 153 square millimeters.
Context
Intel is finalizing die sizes for its next-generation Nova Lake compute tiles, featuring an 8+16 core configuration. Standard tiles measure approximately 110mm², while a premium variant utilizing Big Last Level Cache (bLLC) expands to 150mm². This 36% increase in die area accommodates a massive on-chip cache, rumored at 144MB per tile, designed to address memory latency bottlenecks and directly challenge AMD’s market-leading high-performance gaming and AI processors.
Expected to debut in late 2026 or early 2027, Nova Lake represents a critical strategic pivot for Intel as it leverages advanced manufacturing on the TSMC 2nm and Intel 14A nodes. By integrating bLLC as an answer to AMD’s 3D V-Cache, Intel aims to regain performance leadership in the desktop and enthusiast segments. For investors, these specifications highlight a shift toward specialized silicon configurations that prioritize high-bandwidth data access to support increasingly local AI and gaming demands.
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