Rumor
MediaTek ASIC service fees for Google TPU v8 drop by over fifty percent
Monday, January 26, 2026 at 07:44 AM
A recent UBS report on Google's TPU v8 generation reveals that MediaTek's ASIC design service fee per chip has significantly decreased, falling to less than half of the rates seen in previous generations.
Context
Google is reportedly transitioning its next-generation TPU, codenamed Humufish, to a massive scale that utilizes Intel's EMIB-T packaging technology. This architecture pushes silicon boundaries with a footprint projected at 9-10x the standard reticle size, resulting in a total package area of 13,700 mm². By opting for Intel as the primary packaging partner, Google aims to manage the prohibitive costs associated with high-end alternatives while achieving the extreme density required for advanced generative AI workloads.
This development represents a strategic shift in the semiconductor supply chain, as TSMC's high-cost CoWoS is bypassed in favor of a more economical scaling solution. While TSMC remains a secondary backup with its CoPoS technology, the success of the Humufish project depends heavily on Intel's ability to execute on large-format EMIB-T production. For investors, this highlights Google’s efforts to diversify its hardware ecosystem and provides Intel with a high-profile validation of its advanced packaging roadmap within the competitive AI accelerator market.
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