Rumor

Technical analysis suggests ambitious attempt to use Intel EMIB-T for TSMC CoWoS-L die-to-die interconnects

Monday, March 30, 2026 at 10:50 PM

Discussion regarding technical attempts to integrate CoWoS-L die-to-die interconnects using Intel's EMIB-T packaging technology, highlighting the extreme complexity and ambitious nature of such hybrid packaging solutions.

Context

Technical reports indicate an ambitious move to integrate Intel's EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Vias) into TSMC's CoWoS-L packaging workflows. This cross-vendor integration aims to solve critical bottlenecks in the AI supply chain as TSMC faces extreme capacity constraints for its advanced packaging. By March 2026, TSMC's CoWoS capacity remains fully booked by major players like Nvidia and AMD, forcing secondary vendors to seek hybrid solutions that utilize Intel's domestic packaging facilities in New Mexico and Arizona. This shift is driven by the superior cost-efficiency of EMIB-T, which uses rectangular substrates to reduce material waste compared to TSMC's wafer-based carriers. Analysts estimate that EMIB packaging costs only a few hundred dollars per chip, significantly lower than the $900 to $1,000 cost for CoWoS on high-end processors. If successful, this interoperability could allow customers to fabricate logic at TSMC and package it at Intel, potentially shifting $1 billion in revenue toward Intel Foundry by 2027.

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