Rumor
Intel EMIB packaging faces potential warpage risks from substrate expansion mismatch
Friday, November 28, 2025 at 10:12 AM
Analysis suggests that Intel EMIB technology faces inherent warpage challenges due to the significant thermal expansion coefficient (CTE) mismatch between chips and organic substrates compared to RDL or interposer-based packaging.
Context
A respected advanced-packaging watcher warns that both TSMC’s CoWoS and Intel’s EMIB face significant, underappreciated production risks despite their different architectures. The caution highlights potential “big blunders” in wafer and system-level testing, as well as challenges in fabricating the fine-pitch redistribution layers (RDL) that connect chiplets. This suggests the path to scaling complex AI chip assemblies is fraught with more peril than widely assumed.
This is critical as TSMC’s CoWoS capacity is sold out through 2025 to customers like NVIDIA and AMD, even as it aggressively expands. Any yield drag from these testing or RDL bottlenecks could delay crucial AI accelerator shipments and prolong supply shortages. While Intel’s EMIB has been in high-volume production since 2017, it is not immune to similar interconnect challenges, making manufacturing yield a key risk for investors to monitor across the advanced packaging sector.
Sources (29)
[News] TSMC Set to Expand CoWoS Capacity to Record ...The Future of Advanced Packaging: Intel vs. TSMC2025 Foundry Growth Forecast at 20%, Slowing from 2024CoWoS Capacity Set to Skyrocket by 2026郭明錤 (Ming-Chi Kuo)TSMC outlines work on nine new advanced factories - Taipei TimesReliability Challenges from 2.5D to 3DIC in Advanced ...Test Strategies in the Era of Heterogeneous Integration
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