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MediaTek identifies memory as 50 percent of XPU cost and forecasts massive package size growth
Thursday, February 19, 2026 at 12:38 PM
MediaTek CEO Rick Tsai highlighted that memory now accounts for 50% of XPU bill of materials costs and identified it as a primary bottleneck alongside interconnects and advanced packaging. He noted that while AI training remains HBM-dependent, inference growth is driving demand for high-density DDR DRAM. To address the 'memory wall,' SK hynix and Samsung are developing customized HBM, Processing-in-Memory (PIM), and CXL modules. Furthermore, XPU package sizes are projected to reach up to 20,000 mm² by 2030, utilizing 3D stacking and CoWoS to manage power and thermal demands.
Context
MediaTek CEO Rick Tsai recently identified memory as the primary bottleneck for AI accelerators (XPUs), now accounting for 50% of total bill-of-materials costs. As MediaTek challenges Broadcom in the custom ASIC market—evidenced by its work on Google’s TPU v8—the industry is shifting toward specialized architectures. Major suppliers like SK Hynix and Samsung are responding with custom HBM and processing-in-memory (PIM) to bypass the "memory wall" and optimize power for massive AI workloads.
Furthermore, MediaTek forecasts massive scaling in advanced packaging to meet AI power demands. Utilizing TSMC’s CoWoS technology, XPU package sizes are expected to reach 10,000 mm² by 2030 and potentially scale to 20,000 mm²—roughly the size of a tablet. This trajectory, paired with 3D stacking, indicates that advanced packaging and high-density memory have become the dominant value drivers and cost constraints in the global AI supply chain.
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