Intel 18A process details revealed through Panther Lake, raising yield and technology implementation questions

A detailed technical review of Intel's 18A process, based on the Panther Lake design, discusses key dimensions, GAA pitch, power via implementation, and MEOL/BEOL metal choices. The review highlights that 18A uses HP cells for both logic and SRAM, with a logic minimum pitch of 76nm and SRAM P-P line pitch of 52nm. It notes that 18A SRAM does not use backside power delivery due to GAA spacing constraints, but 14A SRAM will use it via BSCON. The analysis also confirms that 18A's MEOL and BEOL V0/V1 use tungsten, not molybdenum, and M0 metal is copper, which will continue into 14A. The report further points out the presence of an inner spacer in Intel's GAA, contrasting it with Samsung's SF3. Concerns are raised about 18A's current yield situation for Panther Lake, noting that initial mass production is focusing on easier-to-manufacture HP cells at a 36nm minimum pitch, despite Intel's claim of 32nm M0 with single EUV exposure. The large GAA pitch is also discussed in the context of overall process difficulty beyond lithography equipment.