Rumor
AMD Zen 6C compute dies for EPYC Venice expected to double in size compared to Zen 5C
Tuesday, January 6, 2026 at 03:24 AM
An analysis of AMD's upcoming EPYC Venice Zen 6C architecture suggests that the 32-core Zen 6C compute dies (CCDs) will be nearly twice the size of current Zen 5C dies, accompanied by dual I/O dies measuring approximately 375mm² each.
Context
AMD is significantly expanding the scale of its data center offerings with the upcoming EPYC Venice lineup, featuring 32-core Zen 6C compute dies that are nearly double the size of the previous generation. These processors will utilize dual 375mm² I/O dies to support up to 256 cores per socket, a 33% increase in raw core count over the current flagship. Manufactured on TSMC’s 2nm node, the architecture is designed to deliver a 70% generational performance gain while doubling per-socket memory bandwidth to 1.6 TB/s.
This transition is critical for AMD as it defends its market share against Intel and emerging ARM-based rivals in high-growth cloud and AI segments. The 2026 launch timeline aligns with the deployment of next-generation AI accelerators, positioning AMD to offer a high-density, high-bandwidth ecosystem for hyperscale customers. Moving to a larger die footprint and a more advanced process node reflects a strategic focus on maximizing compute density and efficiency for the most demanding enterprise workloads.
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