Rumor
Intel Diamond Rapids Xeon CPUs to utilize separate core and memory hub tiles
Saturday, January 3, 2026 at 09:40 AM
Intel's next-generation Diamond Rapids Xeon processors are expected to utilize a disaggregated chiplet architecture featuring distinct Core Building Block (CBB) and Integrated Memory Hub (IMH) tiles. This design approach indicates a focus on modular tile-based manufacturing for upcoming server platforms.
Context
Intel is transitioning its next-generation Diamond Rapids Xeon CPUs to a disaggregated "tile" architecture, separating the Core Building Block (CBB) from the Integrated Memory Hub (IMH). In a strategic move to prioritize high-bandwidth AI workloads, the company has simplified its roadmap by canceling 8-channel variants to focus exclusively on high-performance 16-channel configurations. This architectural shift aims to eliminate data bottlenecks, supporting MRDIMM Gen 2 speeds of up to 12,800 MT/s and a peak bandwidth of 1.6 TB/s.
Built on the cutting-edge Intel 18A process node, the flagship processors will feature up to 192 Panther Cove-X cores and a 500W TDP. To accelerate AI inference directly on the CPU, Intel is integrating native support for FP8 and TF32 data formats. Scheduled for a 2026 launch, Diamond Rapids is a critical component of Intel's plan to reclaim data center market share from AMD and provide the hardware foundation for future AI cluster build-outs.
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