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Canon adapts nanoimprint lithography for wafer flattening to improve EUV lithography yields
Wednesday, February 4, 2026 at 08:11 PM
Canon has developed a method to apply its nanoimprint lithography technology to semiconductor wafer flattening. By reducing surface irregularities at the nano level, the technology improves the focus of EUV lithography systems and enhances yields for advanced semiconductors. Canon plans to release the equipment by 2027, expanding its business into peripheral manufacturing processes. Intel and Merck have reportedly begun evaluating this technology.
Context
Canon is pivoting its proprietary nanoimprint lithography technology to address a critical bottleneck in advanced chipmaking: wafer surface topography. By applying its "stamping" technique to level out nanometer-scale irregularities, Canon aims to significantly improve the depth of focus for Extreme Ultraviolet (EUV) lithography. This process is designed to boost production yields for the world’s most advanced semiconductors at the 2nm node and beyond, where even microscopic surface warpage can lead to catastrophic patterning defects.
The Japanese firm plans to commercialize this specialized wafer-flattening equipment by 2027, marking a strategic expansion into high-value peripheral semiconductor manufacturing stages. Industry leaders Intel and Merck KGaA have already initiated technical evaluations of the method, signaling strong cross-sector interest from both chipmakers and materials suppliers. If successful, this move allows Canon to capture a vital segment of the logic and memory supply chain by acting as a yield-enhancement partner to existing EUV ecosystems.
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