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Samsung to utilize 1d DRAM node for HBM5E and 2nm process for HBM5 base die
Wednesday, February 25, 2026 at 09:31 AM
Samsung is reportedly planning to utilize its 1d nanometer DRAM node for HBM5E production and will transition to a 2nm process for the HBM5 base die.
Context
As of March 17, 2026, Samsung Electronics is aggressively advancing its high-bandwidth memory roadmap to reclaim leadership in the AI supply chain. The company plans to utilize its sixth-generation 1d DRAM node for the production of HBM5E, while transitioning the critical HBM5 base die to its cutting-edge 2nm logic process. This shift follows Samsung's recent successful yield improvements in 1c DRAM and its deeper R&D collaboration with Applied Materials to optimize sub-2nm Gate-All-Around (GAA) architectures.
Integrating advanced logic nodes into the memory base die is a pivotal architectural change as the industry moves toward Custom HBM. By using a 2nm process for the base die, Samsung aims to address the "memory wall" by improving power efficiency and interconnect density. This strategy positions Samsung to compete for high-volume orders for next-generation AI accelerators, such as future NVIDIA architectures, with mass production of these advanced nodes expected to ramp between 2027 and 2028.
Sources (9)
[PDF] Tokyo Electron IR DaySamsung bets on 1c-nm DRAM to compete with HBM rivals - digitimesThe Memory Wall: Past, Present, and Future of DRAM - SemiAnalysisSamsung HBM4E Base Die Completes Front-End, 2nm Ahead ...Tokyo Electron Investor Relations 2025 | PDF | Microtechnology | Semiconductor Device FabricationSamsung Electronics Teams with Applied Materials to Secure 2nm Process Lead, Bolsters Advanced Node Competitiveness — BigGo Finance[PDF] TECHNOLOGY ROADMAP of DRAM for Three Major manufacturersThe Peak of the AI Memory Supercycle: 5 Decisive Moments for HBM That Will Shake the 2026 Semiconductor Market | Chaos and Order
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