Rumor

Google explores replacing HBM with external DRAM memory pools for TPU v8 using photonic interconnects

Monday, February 2, 2026 at 06:59 AM

Google is reportedly developing a new architecture for its TPU v8 that replaces HBM with independent DRAM memory cabinets connected via photonic technology. This approach addresses HBM capacity shortages and the physical space limitations of motherboard-fixed HBM. The system uses all-optical interconnects via Optical Circuit Switching (OCS) and customized CXL protocols, potentially doubling memory capacity per TPU while reducing reliance on TSMC's CoWoS packaging by freeing up silicon interposer area for compute cores. Lightmatter is identified as a primary supplier for the photonic packaging interfaces.

Context

Google is reportedly planning a radical architecture shift for its TPU v8 chips by 2027, replacing on-package High Bandwidth Memory (HBM) with external DRAM memory pools. This move aims to bypass persistent HBM supply shortages and capacity ceilings imposed by SK Hynix, Samsung, and Micron. By utilizing Lightmatter’s photonic interconnects and Optical Circuit Switching (OCS), Google intends to link TPUs to independent memory cabinets. This disaggregated approach could triple memory capacity from 256GB to over 768GB per TPU while maintaining latency below 100 nanoseconds, a significant improvement over traditional copper-based Ethernet. The strategy reduces reliance on TSMC's CoWoS packaging, as removing HBM from the interposer allows the entire silicon area to be dedicated to compute cores. The architecture introduces a Tier-2 CPU layer for memory management and requires specialized CXL-like chips for synchronization. A final decision on this roadmap is expected by March 5, 2025, with an initial 30% deployment target. If successful, this transition will shift the value chain toward photonic packaging and high-density DRAM modules, challenging the current dominance of HBM in the AI ecosystem.

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