Rumor

Nvidia Rubin Ultra warpage issues may accelerate adoption of CoPoS packaging technology

Tuesday, March 31, 2026 at 01:59 AM

Nvidia is reportedly facing warpage issues during the packaging process of its upcoming Rubin Ultra AI chips. This technical challenge in advanced packaging is expected to accelerate the industry adoption of Chip on Panel on Substrate (CoPoS) technology as a solution for large-scale silicon integration.

Context

Recent reports indicate that Nvidia is facing yield challenges with its upcoming Rubin Ultra AI platform due to significant warpage issues in the packaging process. As interposer sizes grow from 1,700mm² in the Blackwell generation to a massive 9.5X reticle size for Rubin, traditional CoWoS-S (Chip-on-Wafer-on-Substrate) methods are hitting physical limits. This technical bottleneck is expected to accelerate the transition to CoPoS (Chip-on-Panel-on-Substrate), which utilizes square glass or sapphire panels rather than circular silicon wafers to provide better structural integrity and 95% area utilization. While Nvidia officially expects the standard Rubin to enter production in late 2026, the Rubin Ultra—featuring 384GB of HBM4E and 500 billion transistors—is slated for 2027. The shift to panel-level packaging is a critical supply chain pivot involving partners like TSMC, which is currently running pilot lines for 310x310mm panels. If warpage persists, the industry may see a faster-than-anticipated move toward glass substrates, which offer the superior dielectric and thermal stability required for the next generation of trillion-parameter AI models.

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