News
Open access chiplet survey paper details industry developments and Broadcom 3D integration
Saturday, February 28, 2026 at 01:37 AM
A comprehensive open-access chiplet survey paper has been published in IEEE JETCAS, featuring over 200 references and discussing industry implementations including Broadcom 3D integration.
Context
Broadcom has reached a pivotal milestone in the AI supply chain, announcing the first shipments of its 2nm custom compute SoC using proprietary 3.5D eXtreme Dimension System in Package (XDSiP) technology. This development, highlighted in a major IEEE JETCAS survey paper, underscores a shift toward heterogeneous integration where 2.5D and 3D stacking are combined to bypass the physical limits of monolithic chips. By utilizing face-to-face bonding, Broadcom has reportedly reduced die-to-die power consumption by 10x while enabling packages to accommodate over 6,000 mm² of silicon and 12 HBM modules.
For investors, the commercial scale of this technology is the primary driver of value. Broadcom expects to sell at least 1 million 3D stacked chips by 2027, a target that could generate billions in high-margin revenue. Early adopters include Fujitsu, Google, and OpenAI, as the industry moves toward massive gigawatt-scale AI clusters. With AI-related revenue projected to reach $8.2 billion in the first fiscal quarter of 2026, the widespread adoption of Broadcom's stacking architecture positions the company as a critical architect for the next generation of high-performance AI accelerators.
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