News
Samsung unveils 10nm 4F² DRAM prototype using vertical transistors and wafer bonding
Sunday, February 15, 2026 at 12:04 PM
Samsung has demonstrated the feasibility of next-generation 4F² DRAM using Vertical Channel Transistors (VCT) and Wafer-to-Wafer (W2W) Hybrid Copper Bonding (HCB). This 10nm-class 16Gb prototype reduces cell area by 30% and increases productivity per wafer by 20% by stacking cell arrays over peripheral circuits using a 300nm bonding pitch. While reliability was confirmed in a prototype, mass production challenges regarding signal interference and resistance remain.
Context
Samsung Electronics recently demonstrated a breakthrough 10nm-class 4F² DRAM prototype at ISSCC 2026, marking a significant shift in semiconductor scaling. By utilizing Vertical Channel Transistors (VCT), the company has bypassed the physical limitations of traditional horizontal layouts, effectively reducing leakage current. This move is critical as the industry faces diminishing returns from conventional shrinking methods and prepares for the next era of high-density AI memory.
The new 4F² architecture enables a 30% reduction in cell area and a 20% increase in per-wafer productivity. To achieve this, Samsung employed Wafer-to-Wafer Hybrid Copper Bonding, stacking memory cells atop peripheral logic with an industry-leading 300nm bonding pitch. This vertical integration allows for higher-density interconnects than current HBM or NAND standards, though the company must still address signal interference and resistance challenges before mass production.
While the technology is currently in the proof-of-concept stage, it sets a clear trajectory for the future of AI-driven hardware. Samsung targets a performance jump to 10 Gb/s speeds and an efficiency improvement to 2 picojoules per bit by 2030. This innovation positions the company to maintain its competitive edge in the high-performance memory market as data center demands surge.
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