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ASE introduces co-packaged optics technology to address high-density ASIC and optical engine assembly
Thursday, April 2, 2026 at 12:34 AM
ASE Technology has introduced a Co-Packaged Optics (CPO) solution designed to integrate multiple optical engines with an ASIC in a single package. This advancement addresses the assembly complexity of high-bandwidth networking chips by utilizing a large-scale organic substrate to manage high-speed signal integrity and thermal performance.
Context
Advanced Semiconductor Engineering (ASE) has successfully demonstrated a co-packaged optics (CPO) device that integrates multiple optical engines directly onto a substrate with an ASIC. This innovation, part of the VIPack platform, achieves power consumption levels of less than 5pJ/bit by utilizing the shortest possible electrical traces. The solution addresses a critical bottleneck in the AI supply chain: the surge in data center bandwidth demand, which IDC projects will grow at a 24.9% CAGR through 2028.
This technology is pivotal for the semiconductor industry as it transitions from traditional pluggable optics to fully integrated 3D structures. By enabling larger package configurations exceeding 75mm x 75mm, ASE provides a scalable path for high-performance computing to support next-generation networking speeds of 1.6Tb/s and 3.2Tb/s. The deployment of CPO is expected to become a focal point for massive GPU clusters by 2027, as it reduces transmission energy requirements by over 50% compared to standard transceiver solutions.
Sources (5)
ASE Demonstrates CPO that Improves Energy Efficiency for AI applications | ASE HoldingsAdvanced Packaging Evolution: Chiplet and Silicon Photonics-CPO | ASEASE Demonstrates CPO that Improves Energy Efficiency for AI applications | NasdaqCo Packaged Optics (CPO) – Scaling with Light for the Next Wave of InterconnectAdvanced Semiconductor Packaging 2024-2034: Forecasts, Technologies, Applications: IDTechEx
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