News
ASE to launch automated panel-level packaging line by 2026 for AI chips
Thursday, February 5, 2026 at 11:10 AM
ASE is accelerating the development of panel-level packaging for advanced AI semiconductors, aiming to establish a fully automated 310mm x 310mm production line by the end of 2026. This move follows industry trends where Powertech is already utilizing larger 510mm x 515mm panels for clients like AMD and Broadcom, while TSMC develops its own CoPoS technology.
Context
The semiconductor supply chain is pivoting toward Fan-Out Panel-Level Packaging (FOPLP) as TSMC’s CoWoS capacity remains constrained through 2026. ASE Technology is accelerating the completion of a fully automated 310x310mm production line by year-end to align with TSMC’s emerging CoPoS standards. This shift aims to capitalize on the soaring demand for AI and High-Performance Computing chips by improving cost efficiency and surface area utilization, with industry-wide mass production targeted for 2027.
Simultaneously, Powertech Technology is scaling a larger 510x515mm format, securing support from major clients like AMD and Broadcom. The company has committed a massive NT$43.3 billion investment through 2026 to dominate FOPLP capacity. While ASE optimizes for automation and alignment with TSMC, Powertech’s aggressive capital expenditure signals an intense race among Taiwanese OSATs to capture the back-end AI market as chip architectures grow increasingly large and complex.
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