Rumor
SK hynix considers 3nm process for HBM base die to stabilize high-speed power delivery
Thursday, March 19, 2026 at 09:13 AM
SK hynix may transition to a 3nm process for its HBM base die to improve MIM capacitor density, which is critical for stabilizing power control when operating HBM at speeds of 13 to 16 Gbps.
Context
SK hynix is reportedly considering TSMC’s 3nm process for the base logic die of its upcoming HBM4E memory, aiming to stabilize high-speed power delivery. This shift from the 12nm and 5nm nodes used in previous generations is driven by the need for higher capacitance density in Metal-Insulator-Metal (MIM) capacitors. As HBM speeds reach 13—16Gbps, advanced nodes are required to manage extreme transient loads and prevent voltage droop within the shrinking physical footprint of AI accelerators.
This strategic move intensifies the competition with Samsung, which plans to use its own 4nm process for HBM4 and migrate to 2nm by HBM5. SK hynix intends to pair the 3nm logic die with 10nm-class 6th-generation (1c) DRAM for its HBM4E stacks. Mass production for these high-performance components is targeted for 2026 and 2027, specifically to support next-generation AI platforms like NVIDIA’s Vera Rubin Ultra and Google’s custom TPUs.
Sources (8)
SK hynix Partners With TSMC to Strengthen HBM Leadership
Samsung agrees to supply HBM4 to AMD; wider AI chip foundry alliance under discussion - KED GlobalHBM undergoes major architectural shakeup as TSMC and GUC detail HBM4, HBM4E and C-HBM4E — 3nm base dies to enable 2.5x performance boost with speeds of up to 12.8GT/s by 2027 | Tom's Hardware[News] SK hynix Reportedly Weighs TSMC 3nm for HBM4E Logic Dies to Gain Edge over SamsungPower Integrity for NVIDIA H200–Based AI Servers - EE TimesSk Hynix’s AI Strategy: Analysis of Dominance in Semiconductor Memory Chips for AI - Klover.aiSK Hynix Bets on Performance with Next-Gen HBM4E... Considers TSMC's 3nm Process for Logic Die — BigGo FinanceNews - Providing Stable Power for NVIDIA H200: How Capacitors ...
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