Rumor
Upcoming Feynman architecture expected to utilize CoPoS advanced packaging technology
Monday, March 16, 2026 at 09:18 PM
A market observer suggests that the upcoming Feynman architecture is likely to utilize CoPoS packaging technology rather than TSMC's SoIC technology.
Context
At the NVIDIA GTC 2026 conference, CEO Jensen Huang provided the first formal look at the Feynman architecture, a next-generation GPU platform scheduled for release in 2028. Designed as an inference-first chip for autonomous AI agents, Feynman is expected to be manufactured on TSMC’s A16 (1.6nm) process, which utilizes Super Power Rail technology for backside power delivery. Recent industry reports indicate that NVIDIA will likely utilize TSMC’s CoPoS (Chip-on-Panel-on-Substrate) advanced packaging instead of the SoIC standard for this architecture.
The shift to CoPoS marks a radical transition from traditional 300mm circular wafers to 310mm x 310mm rectangular panels. This move is designed to bypass current reticle limits and improve area utilization from 57% to over 87%, significantly reducing edge loss and manufacturing costs for ultra-large AI accelerators. With TSMC planning a pilot line in 2026 and mass production by 2028, the Feynman rollout is expected to drive significant demand for Taiwan’s OSAT and substrate suppliers, including ASE, SPIL, and Nan Ya PCB.
Sources (7)
CoWoS® - Taiwan Semiconductor Manufacturing Company LimitedNvidia bets on AI inference as chip revenue opportunity hits $1 trillion | Reuters[News] NVIDIA May Offer First Look at Feynman at GTC 2026, TSMC A16 and Taiwan Supply Chain in FocusBehind the "CoPoS fever": AI forces semiconductor packaging into the "board-level era"-EEWORLDNVIDIA GTC 2026: Vera Rubin and Feynman Architectures | Let's Data ScienceCoWoS vs. CoPoS vs. CoWoP: TSMC Advanced Packaging Explained - LoveChipUser | times-online.com - TSMC’s CoPoS: The Revolutionary Shift to Rectangular Panel Packaging
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