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TSMC and imec achieve breakthroughs in 0.7nm process technology targeting 2030s CFET production
Wednesday, March 18, 2026 at 08:07 PM
TSMC and research institute imec have achieved progress in 0.7nm semiconductor technology, bringing the mass production of Complementary Field-Effect Transistors (CFET) closer to reality for the 2030s.
Context
The collaboration between TSMC and imec has reached a critical milestone in sub-1nm semiconductor manufacturing, demonstrating the feasibility of the 0.7nm (A7) process node. This breakthrough centers on Complementary Field-Effect Transistors (CFET), an architecture that stacks n-type and p-type transistors vertically to double device density. Recent research confirms a new double-row CFET standard cell design can reduce cell height from 4T to 3.5T, offering a 12.5% area reduction over earlier single-row iterations while optimizing power delivery through backside routing.
This development is vital for the post-2030 roadmap as the industry transitions from Gate-All-Around (GAA) nanosheets, which are expected to peak at the 1.4nm (A14) node. By successfully operating CFET ring oscillators and SRAM bit cells, TSMC is positioning itself to maintain Moore’s Law beyond 2030. These innovations in 3D monolithic stacking and 2D materials like molybdenum disulfide are essential for the next generation of AI and high-performance computing hardware.
Sources (11)
Logic Research at TSMC, page 1-Research-Taiwan Semiconductor Manufacturing Company (TSMC) englishTSMC's Ultimate Favored Technology0.7nm is coming, Imec and Intel: share roadmapImec shows double row CFET standard cell for A7 process node ...Imec Reveals Sub-1nm Transistor Roadmap, 3D-Stacked CMOS 2.0 Plans | Tom's HardwareUnderstanding CFETs, A Next Generation Transistor ArchitectureGAAFET (Gate-All-Around FET) Wiki - SemiWikiTwo-row CFET technology for the A7 technology node
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