News
Samsung shifts FO-PLP form factor to 415x510mm to improve AI chip packaging yield
Wednesday, March 4, 2026 at 01:55 AM
Samsung Electronics is transitioning its Fan-Out Panel-Level Packaging (FO-PLP) from 600x600mm to a smaller 415x510mm form factor to mitigate warpage issues. This shift aims to expand the use of rectangular panels beyond small chips to mobile application processors and AI semiconductors, potentially offering 3x productivity gains over 300mm wafer processes. TSMC is also reportedly developing its own FO-PLP technology using smaller panels. Both companies target 2027 for deployment to reduce reliance on silicon interposers, which currently cause bottlenecks in AI chip manufacturing.
Context
Samsung is pivoting its Fan-Out Panel-Level Package (FO-PLP) strategy by shifting from 600x600mm panels to a smaller 415x510mm form factor. This move specifically targets chronic warpage issues that have historically hindered yields in larger rectangular panels. By optimizing the size, Samsung expects a 3x productivity gain over traditional 300mm wafer-based processes. Crucially, this technology reduces the industry's reliance on silicon interposers—a primary bottleneck in the current AI chip and HBM supply chain—by moving more of the process to the back-end.
The transition places Samsung in a direct race with TSMC, which is also developing smaller-format FO-PLP technology to supplement its capacity-constrained CoWoS lines. These next-generation packaging solutions are vital for scaling AI accelerators and mobile processors more cost-effectively than current 2.5D methods. While both companies are targeting a 2027 deployment, Samsung is reportedly pushing for an earlier mass production timeline to capture market share in the high-performance computing sector.
Related Companies
TSMC
2330
S
Samsung