Rumor
Chip designs see increased power/ground connections and pin speeds, likely for high-performance computing
Monday, February 9, 2026 at 08:56 AM
The tweet discusses the increasing complexity of chip designs, specifically regarding power and ground connections. It also mentions a significant increase in pin speed from 8Gbps to 11Gbps, attributed to "革ジャン" (Kakujan), which is a common Japanese nickname for NVIDIA's CEO, Jensen Huang. This implies a focus on high-performance memory or interconnects, likely relevant to AI infrastructure or advanced computing.
Context
Recent reports from technical supply chain sources indicate that Nvidia CEO Jensen Huang has significantly escalated technical requirements for next-generation AI hardware, specifically targeting a per-pin speed of 11Gbps. This figure represents a massive "crazy" leap from initial industry projections, which had anticipated a drop from 8Gbps to 6Gbps to manage thermal and electrical stability. This aggressive shift is aimed at maximizing bandwidth for high-performance computing (HPC) and generative AI workloads, effectively forcing suppliers to overcome substantial engineering hurdles.
To support these extreme speeds and the resulting thermal load, the physical design of upcoming chips is seeing a near-doubling of power and ground connections. This increased pin density is essential for the Blackwell Ultra and upcoming Rubin architectures, which are expected to draw between 1,200W and 2,700W per module. Investors should view this as a clear signal that Nvidia is doubling down on a "performance-at-all-costs" strategy, prioritizing hardware dominance even as it pushes the limits of power delivery and liquid cooling infrastructure for 2025 and 2026 deployments.
Sources (1)
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