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Canon and Synopsys Japan to develop 2nm image processing SoC design technology using Rapidus foundry services
Tuesday, March 3, 2026 at 08:40 AM
As part of the Ministry of Economy, Trade and Industry and NEDO Post-5G project, Synopsys Japan and Canon are developing design technology for image processing SoCs using 2nm-generation processes. The project will leverage Rapidus for 2nm Gate-All-Around (GAA) processes and chiplet technology.
Context
Canon and Synopsys have been selected by Japan’s NEDO to lead a strategic project under the Post-5G infrastructure enhancement program. The collaboration focuses on developing advanced System-on-Chip (SoC) design technology specifically for high-efficiency image processing. By leveraging 2nm process technology and sophisticated chiplet integration, the partners aim to overcome the physical and power limitations of traditional single-chip architectures.
This initiative is critical for securing Japan’s semiconductor supply chain as demand for real-time AI processing surges in autonomous driving, smart cities, and IoT. Synopsys will provide the essential EDA design tools and IP, while Canon integrates its proprietary imaging expertise and manufacturing capabilities. The project is set for a 5-year development cycle, targeting a platform that delivers high-performance data processing with significantly reduced power consumption. This partnership underscores a major push toward domestic self-sufficiency in the next-generation silicon market.
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