Rumor

NVIDIA Rubin Ultra production forecast to require up to 20,000 N3 wafers for HBM base dies

Monday, March 23, 2026 at 09:48 PM

Production of NVIDIA Rubin Ultra GPUs is expected to require the reservation of 10,000 to 20,000 TSMC N3 wafers specifically for HBM base dies. However, anticipated yield losses during the stacking process are likely to result in wafer scrapping and margin compression for memory suppliers. The industry is watching how major HBM providers like SK hynix and Micron will manage these yield and cost challenges.

Context

As NVIDIA transitions its AI infrastructure to the Vera Rubin platform announced in March 2026, the supply chain faces a critical shift in high-bandwidth memory architecture. The Rubin Ultra GPU, which delivers up to 50 petaflops of inference performance, requires HBM4 memory utilizing advanced logic base dies. Reports indicate NVIDIA may need to reserve between 10,000 and 20,000 of TSMC’s N3 (3nm) wafers specifically for these base dies to meet production forecasts. This move signifies a departure from traditional DRAM-based processes toward high-performance logic nodes for memory controllers. This transition presents significant manufacturing risks for partners SK Hynix and Micron, who are collaborating with TSMC on the 3nm base die integration. While the N3P node offers a 20-30% performance boost, the complexity of stacking 12-hi or 16-hi DRAM layers onto logic wafers is expected to cause margin compression. Investors are closely monitoring potential wafer scrapping and yield losses during the CoWoS packaging phase, as the industry enters a high-stakes silicon shortage where TSMC's leading-edge capacity remains the primary bottleneck for global AI scaling.

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